The present invention relates to a current-switching type logic circuit, and more particularly to a current-switching type compound semiconductor logic circuit which is high in an operating speed and low in power consumption.
There has been a great demand for a higher-speed information processing apparatus as an information-oriented society develops, and a higher-speed operation is required for a semiconductor device constituting the information processing apparatus. In order to meet with the requirement, semiconductor devices employing various compound semiconductors whose electron mobility is high have been developed in place of conventional semiconductor devices containing silicon as a main component, and the semiconductor devices have been applied to high-speed operating logic circuits or the like.
Nest, referring to FIG. 1, an invertor circuit constituted by an SCFL (source coupled FET logic) circuit employing a GaAs IC will be described as a conventional example of such a semiconductor device.
In FIG. 1, reference numeral 41 designates a source follower circuit section; 42, a switching section; 43 and 44, source follower transistors; 45 and 46, level-shifting diodes; 47 and 48, constant-current supply transistors; 49 and 50, load elements; 51 and 52, driving transistors; 53, a current source; 54 and 55, power source terminals; 56 and 57, input terminals; and 58 and 59, output terminals.
Generally, depletion-type transistors are employed in an SCFL circuit. The source follower circuit section 41 is provided because it is necessary to make the potential level of an output signal of the SCFL circuit lower than that of the drain terminal of each of the driving transistors in view of the matching property with a logic circuit in the succeeding stage. In this circuit, the level shifting of signal is performed by the gate-source voltage of each of the source follower transistors 43 and 44 and by a voltage drop across each of the level-shifting diodes 45 and 46.
The high-speed operation and reduction of power consumption of a logic circuit device are being attained by using a compound semiconductor as described above. In the compound semiconductor, however, it is disadvantageous in that the frequency characteristics of transistors are deteriorated because of an existence of unnecessary energy level.
It is considered that this problem is caused by the fact that no insulator, for example, a silicon oxide (SiO) for silicon, for forming a stable interface has been found and the composition of the compound semiconductor is hardly stabilized because it is composed of a plurality of elements.
There has been a problem in that unnecessary energy level may occur due to the foregoing reason thereby resulting in repeating charge and discharge whenever the potential level changes so that the frequency characteristics of transistors are deteriorated. This is so-called "drain-lag" which has also been discussed in a publication "IEEE J. of SSC Vo. 23, No. 2, 1988".
The above described deterioration of the frequency characteristics will be described hereinbelow with reference to the waveform diagram shown in FIG. 2.
First, in a first state having a duty ratio of 50% where a high level and a low level appear repeatedly at a predetermined interval, generated is an output signal having a waveform which is obtained by inverting the input signal without delay. Next, in a second state where the input signal continues to be in a low level for a long period of time and is then changed to be in a high level, there occurs a time lag between the changes in the signal levels of the input and output signals. More specifically, in the second state, after the input signal varies from the low level to the high level, the output signal varies from the high level to the low level with the time lag. In a third state where the input signal continues to be in a high level for a long time and is then changed to be in a low level, on the contrary, there occurs a time lag between the changes in the signal levels of the input and output signals. More specifically, in the third state, after the input signal varies from the high level to the low level, the output signal varies from the low level to the high level with the time lag. the jitter interval is changed between the leading and trailing edges of the input signal, the deterioration of the frequency characteristics appears as a variation of a cross point.